Linear-Digital ICs

MCQsQuestion.com has 49 Question/Answers about Topic Linear-Digital ICs

Which of the following require(s) interfacing circuitry?

Which of the following require(s) interfacing circuitry?
  • A. Keyboards
  • B. Video terminals
  • C. Printers
  • D. All of the above
  • Correct Answer: Option D

For the RS-232C circuit, ________ is a mark and ________ is a space.

For the RS-232C circuit, ________ is a mark and ________ is a space.
  • A. 12 V, –12 V
  • B. –12 V, 12 V
  • C. 5 V, 0 V
  • D. –5 V, 0 V
  • Correct Answer: Option B

For transistor transistor logic (TTL) circuits, ________ is a mark and ________ is a space.

For transistor transistor logic (TTL) circuits, ________ is a mark and ________ is a space.
  • A. 12 V, 0 V
  • B. 0 V, 12 V
  • C. 0 V, 5 V
  • D. 5 V, 0 V
  • Correct Answer: Option D

In interfacing circuitry, a receiver provides ________ input impedance to minimize loading of the input signal.

In interfacing circuitry, a receiver provides ________ input impedance to minimize loading of the input signal.
  • A. high
  • B. medium
  • C. low
  • D. zero
  • Correct Answer: Option A

An input at a frequency of 1070 Hz will drive the decoder output voltage to ________.

An input at a frequency of 1070 Hz will drive the decoder output voltage to ________.
  • A. –5 V
  • B. 14 V
  • C. –5 V and 14 V
  • D. None of the above
  • Correct Answer: Option B

The free-running frequency of a 565 FSK decoder is adjusted with ________.

The free-running frequency of a 565 FSK decoder is adjusted with ________.
  • A. external capacitors
  • B. an external resistor
  • C. an external RC network
  • D. an internal clock
  • Correct Answer: Option B

In the frequency-shift keyed (FSK) signal decoder, the RC ladder filter is used to ________.

In the frequency-shift keyed (FSK) signal decoder, the RC ladder filter is used to ________.
  • A. remove the difference frequency component
  • B. remove the sum frequency component
  • C. remove both the difference and the sum frequency components
  • D. None of the above
  • Correct Answer: Option B

When the loop is in lock in a PLL, the input frequency is ________ the output frequency from the VCO.

When the loop is in lock in a PLL, the input frequency is ________ the output frequency from the VCO.
  • A. the same as
  • B. greater than
  • C. smaller than
  • D. None of the above
  • Correct Answer: Option A

A phase-locked loop (PLL) is an electronic circuit that consists of ________.

A phase-locked loop (PLL) is an electronic circuit that consists of ________.
  • A. a phase detector
  • B. a low-pass filter
  • C. a voltage-controlled oscillator
  • D. All of the above
  • Correct Answer: Option D

The frequency of the 566 VCO is set by ________.

The frequency of the 566 VCO is set by ________.
  • A. an external resistor
  • B. an external capacitor
  • C. both an external resistor and an external capacitor
  • D. None of the above
  • Correct Answer: Option C

A voltage-controlled oscillator (VCO) is a circuit that provides a ________ output signal.

A voltage-controlled oscillator (VCO) is a circuit that provides a ________ output signal.
  • A. zero
  • B. varying
  • C. constant
  • D. None of the above
  • Correct Answer: Option B

Time periods for monostable operation of the 555 timer can range from ________ to ________, making this IC useful for a range of applications.

Time periods for monostable operation of the 555 timer can range from ________ to ________, making this IC useful for a range of applications.
  • A. picoseconds, nanoseconds
  • B. nanoseconds, milliseconds
  • C. microseconds, many seconds
  • D. None of the above
  • Correct Answer: Option C

In astable operation of the 555 timer, the lower and upper peaks of the charging/discharging external capacitor are ________ to ________.

In astable operation of the 555 timer, the lower and upper peaks of the charging/discharging external capacitor are ________ to ________.
  • A. –VCC, VCC
  • B. –0.5 VCC, 0.5 VCC
  • C. 1/3 VCC, 1/2 VCC
  • D. 1/3 VCC, 2/3 VCC
  • Correct Answer: Option D

In a 555 timer, a series connection of three resistors sets the reference voltage levels to the two comparators at ________ and ________.

In a 555 timer, a series connection of three resistors sets the reference voltage levels to the two comparators at ________ and ________.
  • A. 2VCC / 3, VCC / 3
  • B. VCC / 2, VCC / 4
  • C. VCC, VCC / 2
  • D. VCC, VCC
  • Correct Answer: Option A

The conversion resolution of an 8-stage counter operating an 8-stage ladder network using a reference voltage of 5 V is ________.

The conversion resolution of an 8-stage counter operating an 8-stage ladder network using a reference voltage of 5 V is ________.
  • A. 0.0195 mV
  • B. 0.195 mV
  • C. 1.95 mV
  • D. 19.5 mV
  • Correct Answer: Option D
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