DC Biasing-FETs

MCQsQuestion.com has 31 Question/Answers about Topic DC Biasing-FETs

In p-channel FETs, the level of VGS is ________ while the level of VDS is ________.

In p-channel FETs, the level of VGS is ________ while the level of VDS is ________.
  • A. negative, negative
  • B. positive, positive
  • C. negative, positive
  • D. positive, negative
  • Correct Answer: Option D

In a universal JFET bias curve, the vertical scale labeled M is used for finding the solution to the ________ configuration.

In a universal JFET bias curve, the vertical scale labeled M is used for finding the solution to the ________ configuration.
  • A. fixed-bias
  • B. self-bias
  • C. voltage-divider
  • D. None of the above
  • Correct Answer: Option C

In a universal JFET bias curve, the vertical scale labeled m is used to find the solution to the ________ configuration.

In a universal JFET bias curve, the vertical scale labeled m is used to find the solution to the ________ configuration.
  • A. fixed-bias
  • B. self-bias
  • C. voltage-divider
  • D. None of the above
  • Correct Answer: Option A

The level of VDS is typically between ________ % and ________ % of VDD.

The level of VDS is typically between ________ % and ________ % of VDD.
  • A. 0, 100
  • B. 10, 90
  • C. 25, 75
  • D. None of the above
  • Correct Answer: Option C

________ must be considered in the total design process.

________ must be considered in the total design process.
  • A. Dc conditions
  • B. Level of amplification
  • C. Signal strength
  • D. All of the above
  • Correct Answer: Option D

For R2 smaller than ________ k the voltage VD is equal to VDD = 16 V.

For R2 smaller than ________ k the voltage VD is equal to VDD = 16 V.
  • A. 3.75
  • B. 5
  • C. 12.0
  • D. 24
  • Correct Answer: Option A

In a feedback-bias configuration, the slope of the dc load line is controlled by ________.

In a feedback-bias configuration, the slope of the dc load line is controlled by ________.
  • A. RG
  • B. RD
  • C. VDG
  • D. None of the above
  • Correct Answer: Option B

Specification sheets typically provide ________ for enhancement-type MOSFETs.

Specification sheets typically provide ________ for enhancement-type MOSFETs.
  • A. the threshold voltage VGS(Th)
  • B. a level of drain current ID(on)
  • C. an ID(on)
  • D. All of the above
  • Correct Answer: Option D

In an enhancement-type MOSFET, the drain current is zero for levels of VGS less than the ________ level.

In an enhancement-type MOSFET, the drain current is zero for levels of VGS less than the ________ level.
  • A. VGS(Th)
  • B. VGS(off)
  • C. VP
  • D. VDD
  • Correct Answer: Option A

In ________ configuration(s) a depletion-type MOSFET can operate in enhancement mode.

In ________ configuration(s) a depletion-type MOSFET can operate in enhancement mode.
  • A. self-bias
  • B. fixed-bias with no VGG
  • C. voltage-divider
  • D. None of the above
  • Correct Answer: Option C

In a depletion-type MOSFET, the transfer characteristic rises ________ as VGS becomes more positive.

In a depletion-type MOSFET, the transfer characteristic rises ________ as VGS becomes more positive.
  • A. less rapidly
  • B. more rapidly
  • C. the same
  • D. None of the above
  • Correct Answer: Option B

________ levels of RS result in ________ quiescent values of ID and ________ negative values of VGS.

________ levels of RS result in ________ quiescent values of ID and ________ negative values of VGS.
  • A. Increased, lower, less
  • B. Increased, higher, less
  • C. Increased, higher, more
  • D. Increased, less, lower
  • Correct Answer: Option A

The slope of the dc load line in a self-bias configuration is controlled by ________.

The slope of the dc load line in a self-bias configuration is controlled by ________.
  • A. VDD
  • B. RD
  • C. RG
  • D. RS
  • Correct Answer: Option D

The dc load line is drawn using the equation obtained by applying Kirchhoff’s voltage law (KVL) at ________ side loop(s) of the circuit.

The dc load line is drawn using the equation obtained by applying Kirchhoff’s voltage law (KVL) at ________ side loop(s) of the circuit.
  • A. the output
  • B. the input
  • C. both the input and output
  • D. None of the above
  • Correct Answer: Option B

When plotting the transfer characteristics, choosing VGS = 0.5VP will result in a drain current level of ________ IDSS.

When plotting the transfer characteristics, choosing VGS = 0.5VP will result in a drain current level of ________ IDSS.
  • B. 0.25
  • C. 0.5
  • D. 1
  • Correct Answer: Option B
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