Shift Registers

MCQsQuestion.com has 55 Question/Answers about Topic Shift Registers

To shift data from right side to shift register SH/LD pin must be equal to

To shift data from right side to shift register SH/LD pin must be equal to
  • B. 1
  • C. 2
  • D. None
  • Correct Answer: Option C

When J and complement of K are 1, flip-flop QA after shift is equal to

When J and complement of K are 1, flip-flop QA after shift is equal to
  • A. 1
  • C. reset
  • D. defined
  • Correct Answer: Option A

Assume a LOW logic level is placed on the SHIFT/LOAD input of a 74195 shift register. The output will change ________.

Assume a LOW logic level is placed on the SHIFT/LOAD input of a 74195 shift register. The output will change ________.
  • A. immediately
  • B. if the CLOCK is also LOW
  • C. on the next clock leading edge
  • D. depending on the J and K inputs
  • Correct Answer: Option C

Assume a 4-bit Johnson counter is initially cleared. After the first clock pulse the output is 0001. After the next clock pulse the output will be ________.

Assume a 4-bit Johnson counter is initially cleared. After the first clock pulse the output is 0001. After the next clock pulse the output will be ________.
  • A. 0011
  • B. 0010
  • C. 1000
  • D. 0110
  • Correct Answer: Option A

A Johnson counter, constructed with N flip-flops, has how many unique states?

A Johnson counter, constructed with N flip-flops, has how many unique states?
  • A. N
  • B. 2N
  • C. 2N
  • D. N2
  • Correct Answer: Option B

A 4-bit ring counter is loaded with a single 1. The frequency of any given output is ________.

A 4-bit ring counter is loaded with a single 1. The frequency of any given output is ________.
  • A. the same as the clock
  • B. twice the clock frequency
  • C. one-half the clock frequency
  • D. one-fourth the clock frequency
  • Correct Answer: Option D

An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.

An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.
  • A. QE
  • B. QF
  • C. QG
  • D. QH
  • Correct Answer: Option A

Shifting a binary number to the left by one position is equivalent to ________.

Shifting a binary number to the left by one position is equivalent to ________.
  • A. multiplying by two
  • B. multiplying by four
  • C. dividing by two
  • D. dividing by four
  • Correct Answer: Option A

A type of shift register that requires access to the Q outputs of all stages is ________.

A type of shift register that requires access to the Q outputs of all stages is ________.
  • A. parallel in/serial out
  • B. serial in/parallel out
  • C. serial in/serial out
  • D. a bidirectional shift register
  • Correct Answer: Option B

A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________.

A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________.
  • A. parallel in/serial out
  • B. serial in/parallel out
  • C. serial in/serial out
  • D. parallel in/parallel out
  • Correct Answer: Option D

Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?

Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?
  • B. 1
  • C. 2
  • D. 3
  • Correct Answer: Option B

Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the QH output?

Assume an 8-bit serial in/parallel out shift register needs to be cleared but has no clear input. How many clock cycles are required before a zero applied to the input appears on the QH output?
  • A. 1
  • B. 7
  • C. 8
  • D. 9
  • Correct Answer: Option C

When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.

When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.
  • A. 40 kHz
  • B. 50 kHz
  • C. 400 kHz
  • D. 500 kHz
  • Correct Answer: Option C

A modulus-12 ring counter requires a minimum of ________.

A modulus-12 ring counter requires a minimum of ________.
  • A. 10 flip-flops
  • B. 12 flip-flops
  • C. 6 flip-flops
  • D. 2 flip-flops
  • Correct Answer: Option B

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?
  • A. 1.67 s
  • B. 26.67 s
  • C. 26.7 ms
  • D. 267 ms
  • Correct Answer: Option B
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