Digital System Projects Using HDL

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In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.

In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.
  • A. BCD counters
  • B. system clock signal
  • C. display register
  • D. decoder/display
  • Correct Answer: Option B

The timing and control block provides the ________ for the frequency counter.

The timing and control block provides the ________ for the frequency counter.
  • A. brains
  • B. BCD counters
  • C. display register
  • D. six different frequency measurement ranges
  • Correct Answer: Option A

In the frequency counter, the length of time for the ________ to be enabled can be selected with the range select input.

In the frequency counter, the length of time for the ________ to be enabled can be selected with the range select input.
  • A. display register
  • B. frequency prescaler
  • C. BCD counter
  • D. signal generator
  • Correct Answer: Option C

The major blocks of the frequency counter are the counter, ________, decoder/display, and the timing and control unit.

The major blocks of the frequency counter are the counter, ________, decoder/display, and the timing and control unit.
  • A. signal prescaler
  • B. control inputs
  • C. signal generator
  • D. display register
  • Correct Answer: Option D

VARIABLES are considered to be updated ________ within a sequence of statements in a PROCESS, whereas SIGNALS referred to in a PROCESS are updated when the PROCESS ________.

VARIABLES are considered to be updated ________ within a sequence of statements in a PROCESS, whereas SIGNALS referred to in a PROCESS are updated when the PROCESS ________.
  • A. once, starts
  • B. immediately, suspends
  • C. twice, ends
  • D. never, starts
  • Correct Answer: Option B

In the digital clock project HDL code, the MOD-12 counter is using ________.

In the digital clock project HDL code, the MOD-12 counter is using ________.
  • A. a BCD counter followed by a MOD-2 counter
  • B. a single HDL module
  • C. a MOD-6 counter followed by a MOD-2 counter
  • D. a MOD-12 counter followed by a D flip-flop
  • Correct Answer: Option B

In the digital clock project, a 60 pps input is transformed into a 1 pps timing signal. The block is called ________.

In the digital clock project, a 60 pps input is transformed into a 1 pps timing signal. The block is called ________.
  • A. a BCD counter
  • B. a MOD-60 counter
  • C. frequency divider
  • D. frequency prescaling
  • Correct Answer: Option D

In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input is active. On the next clock pulse the AM/PM flip-flop will ________.

In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input is active. On the next clock pulse the AM/PM flip-flop will ________.
  • A. set
  • B. reset
  • C. toggle
  • D. clear
  • Correct Answer: Option C

In the digital clock design, the hours section is different from the seconds and minutes section in that it never goes to ________.

In the digital clock design, the hours section is different from the seconds and minutes section in that it never goes to ________.
  • A. the 0 state
  • B. 13
  • C. the ring counter
  • D. the BCD counter
  • Correct Answer: Option A

In the digital clock project, the 1 pps signal is used as a synchronous clock for all of the counter stages, which are ________.

In the digital clock project, the 1 pps signal is used as a synchronous clock for all of the counter stages, which are ________.
  • A. advanced BCD counters
  • B. MOD-6 counters
  • C. synchronous cascaded
  • D. 1 pulse per second
  • Correct Answer: Option C

In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of ________.

In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of ________.
  • A. 1 pps
  • B. 60 pps
  • C. 100 pps
  • D. 600 pps
  • Correct Answer: Option B

In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state.

In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state.
  • A. 0 hex
  • B. 4 hex
  • C. 8 hex
  • D. F hex
  • Correct Answer: Option D

In the keypad encoder, the ring counter is implemented using ________ that responds to the clk input.

In the keypad encoder, the ring counter is implemented using ________ that responds to the clk input.
  • A. SIGNAL
  • B. FUNCTION
  • C. CASE
  • D. PROCESS
  • Correct Answer: Option D

In the keypad encoder, the ________ detects when a key is pressed.

In the keypad encoder, the ________ detects when a key is pressed.
  • A. ring counter
  • B. MOD-6 counter
  • C. BCD counter
  • D. freeze bit
  • Correct Answer: Option D

The step rate of the simulation of a stepper motor is probably ________ the actual stepper motor.

The step rate of the simulation of a stepper motor is probably ________ the actual stepper motor.
  • A. slower than
  • B. more than
  • C. almost the same as
  • D. exactly the same as
  • Correct Answer: Option A
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