Counters

MCQsQuestion.com has 87 Question/Answers about Topic Counters

The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ________.

The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ________.
  • A. 10%
  • B. 20%
  • C. 50%
  • D. 80%
  • Correct Answer: Option B

Assume you want to determine the timing diagram for a 4-bit counter using an oscilloscope. The best choice for an oscilloscope trigger signal is ________.

Assume you want to determine the timing diagram for a 4-bit counter using an oscilloscope. The best choice for an oscilloscope trigger signal is ________.
  • A. the most significant bit (MSB)
  • B. the least significant bit (LSB)
  • C. the clock signal
  • D. from a composite of the MSB and LSB
  • Correct Answer: Option C

A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because ________.

A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because ________.
  • A. it is a random event
  • B. it occurs less frequently than the normal decoded output
  • C. it is very fast
  • D. all of the above
  • Correct Answer: Option D

A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.

A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.
  • A. J and K inputs must both = 0
  • B. J must be 0, K doesn't matter
  • C. J doesn't matter, K must = 0
  • D. J must be 0 and K must be 1
  • Correct Answer: Option B

The minimum number of flip-flops that can be used to construct a modulus-5 counter is ________.

The minimum number of flip-flops that can be used to construct a modulus-5 counter is ________.
  • A. 3
  • B. 5
  • C. 8
  • D. 10
  • Correct Answer: Option A

Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up.” The third and fourth stages will ________.

Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up.” The third and fourth stages will ________.
  • A. continue to count with correct outputs
  • B. continue to count but have incorrect outputs
  • C. stop counting
  • D. turn into molten silicon
  • Correct Answer: Option C

A D flip-flop can be made to toggle by ________.

A D flip-flop can be made to toggle by ________.
  • A. connecting to to D
  • B. connecting to Q to D
  • C. connecting D low
  • D. connecting D high
  • Correct Answer: Option A

The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.

The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.
  • A. 8
  • B. 15
  • C. 16
  • D. 32
  • Correct Answer: Option B

A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.

A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.
  • A. 1.25 kHz
  • B. 2.50 kHz
  • C. 160 kHz
  • D. 320 kHz
  • Correct Answer: Option A

An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________.

An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________.
  • A. taking the output on the other side of the flip-flops ( instead of Q)
  • B. clocking of each succeeding flip-flop from the other side ( instead of Q)
  • C. changing the flip-flops to trailing edge triggering
  • D. all of the above
  • Correct Answer: Option D

An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?

An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
  • A. None
  • B. One
  • C. Two
  • D. Fifteen
  • Correct Answer: Option D

The hexadecimal equivalent of 15,536 is ________.

The hexadecimal equivalent of 15,536 is ________.
  • A. 3CB0
  • B. 3C66
  • C. 63C0
  • D. 6300
  • Correct Answer: Option A

Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?

Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?
  • A. 50,000
  • B. 65,536
  • C. 25,536
  • D. 15,536
  • Correct Answer: Option D

Three cascaded decade counters will divide the input frequency by ________.

Three cascaded decade counters will divide the input frequency by ________.
  • A. 10
  • B. 20
  • C. 100
  • D. 1,000
  • Correct Answer: Option D

A counter with a modulus of 16 acts as a ________.

A counter with a modulus of 16 acts as a ________.
  • A. divide-by-8 counter
  • B. divide-by-16 counter
  • C. divide-by-32 counter
  • D. divide-by-64 counter
  • Correct Answer: Option B
Page 1 of 612345...Last »