To shift data from right side to shift register SH/LD pin must be equal to

To shift data from right side to shift register SH/LD pin must be equal to
  • B. 1
  • C. 2
  • D. None
  • Correct Answer: Option C

When J and complement of K are 1, flip-flop QA after shift is equal to

When J and complement of K are 1, flip-flop QA after shift is equal to
  • A. 1
  • C. reset
  • D. defined
  • Correct Answer: Option A

Assertion (A): The resolution of a DAC depends on the number of bits Reason (R): Low resolution leads to fine control.

Assertion (A):  The resolution of a DAC depends on the number of bits Reason (R): Low resolution leads to fine control.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B

Assertion (A): In a serial in-serial out shift register, access is available only to the left most or right most flip flops Reason (R): If the output of a shift register is feedback to serial input it can be used as a ring counter.

Assertion (A):  In a serial in-serial out shift register, access is available only to the left most or right most flip flops Reason (R): If the output of a shift register is feedback to serial input it can be used as a ring counter.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B

Assertion (A): In a parallel in-serial out shift register data is loaded one bit-at a timeReason (R): A serial in-serial out shift register can be used to introduce a time delay.

Assertion (A):  In a parallel in-serial out shift register data is loaded one bit-at a timeReason (R): A serial in-serial out shift register can be used to introduce a time delay.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option D

Assertion (A): Divide-64 counter is a Mod-64 counter and divides the input frequency by 64 Reason (R): A Mod 64 counter can be obtained by cascading Mod 16 and Mod 4 counters.

Assertion (A):  Divide-64 counter is a Mod-64 counter and divides the input frequency by 64 Reason (R): A Mod 64 counter can be obtained by cascading Mod 16 and Mod 4 counters.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B

Assertion (A): A presettable counter can be preset to any desired starting pointReason (R): The maximum frequency of a ripple counter depends on the modulus.

Assertion (A):  A presettable counter can be preset to any desired starting pointReason (R): The maximum frequency of a ripple counter depends on the modulus.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B

Assertion (A): An SR latch has the problem of RAC conditionReason (R): While designing a digital circuit RAC condition should be avoided.

Assertion (A):  An SR latch has the problem of RAC conditionReason (R): While designing a digital circuit RAC condition should be avoided.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B

Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

Assertion (A):  A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B

Assertion (A): A multiplexer can be used for data routing.Reason (R): A multiplexer has one input and many outputs.

Assertion (A):  A multiplexer can be used for data routing.Reason (R): A multiplexer has one input and many outputs.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option C

Assertion (A): An encoder converts key dips to binary code.Reason (R): An encoder has more inputs than output.

Assertion (A):  An encoder converts key dips to binary code.Reason (R): An encoder has more inputs than output.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B

Assertion (A): In a BCD to 7 segment decoder the number of outputs active at one time is always the same.Reason (R): A decoder can be used to interface BCD input to LED display.

Assertion (A):  In a BCD to 7 segment decoder the number of outputs active at one time is always the same.Reason (R): A decoder can be used to interface BCD input to LED display.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option D

Assertion (A): In a magnitude comparator IC the cascading inputs provide a means to cascade the 4 bit comparators Reason (R): A magnitude comparator has three outputs, A = B, A > B and A < B

Assertion (A):  In a magnitude comparator IC the cascading inputs provide a means to cascade the 4 bit comparators Reason (R): A magnitude comparator has three outputs, A = B, A > B and A < B
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B

Assertion (A): A high density IC has more diodes, transistors and resistors per unit surface area.Reason (R): A high density IC can handle high voltages.

Assertion (A):  A high density IC has more diodes, transistors and resistors per unit surface area.Reason (R): A high density IC can handle high voltages.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option C

Assertion (A): Power drain of CMOS increases with operating frequency Reason (R): All unused CMOS inputs should be tied either to a fixed voltage level (0 or VDD) or to another input.

Assertion (A):  Power drain of CMOS increases with operating frequency Reason (R): All unused CMOS inputs should be tied either to a fixed voltage level (0 or VDD) or to another input.
  • A. Both A and R are correct and R is correct explanation of A
  • B. Both A and R are correct but R is not correct explanation of A
  • C. A is true, R is false
  • D. A is false, R is true
  • Correct Answer: Option B