pipelining in computer architecture

MCQsQuestion.com has 16 Question/Answers about Topic pipelining in computer architecture

If any instruction in A1, . . . , A4, D, M1, . . . , M7 has same register destination as this instruction, then possible solution is

If any instruction in A1, . . . , A4, D, M1, . . . , M7 has same register destination as this instruction, then possible solution is
  • A. Stalling issue of instruction in ID
  • B. Stalling issue of instruction in EX
  • C. Stalling issue of instruction in DEC
  • D. Stalling issue of instruction in MEM
  • Correct Answer: Option A

If some combination of instructions cannot be accommodated because of resource conflicts, processor is said to have a

If some combination of instructions cannot be accommodated because of resource conflicts, processor is said to have a
  • A. Data hazard
  • B. Structural hazard
  • C. Pipeline hazard
  • D. Stall
  • Correct Answer: Option B

Time required between moving an instruction one step down pipeline is a

Time required between moving an instruction one step down pipeline is a
  • A. Clock cycle
  • B. Hit rate
  • C. Cycle rate
  • D. Processor cycle
  • Correct Answer: Option D

When compiler attempts to schedule instructions to avoid hazard; this approach is called

When compiler attempts to schedule instructions to avoid hazard; this approach is called
  • A. Compiler
  • B. Static scheduling
  • C. Dynamic scheduling
  • D. Both a and b
  • Correct Answer: Option D

Delays arising from use of a load result 1 or 2 cycles after loads, refers as

Delays arising from use of a load result 1 or 2 cycles after loads, refers as
  • A. Data stall
  • B. Control stall
  • C. Branch stall
  • D. Load stall
  • Correct Answer: Option D

Simplest scheme to handle branches is to

Simplest scheme to handle branches is to
  • A. Flush pipeline
  • B. Freezing pipeline
  • C. Depth of pipeline
  • D. Both a and b
  • Correct Answer: Option D

Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and relative frequencies of these operations are 40%, 20%, and 40%, respectively, then average instruction execution time on unpipelined processor is

Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and relative frequencies of these operations are 40%, 20%, and 40%, respectively, then average instruction execution time on unpipelined processor is
  • A. 4.4 ns
  • B. 4.2 ns
  • C. 3.4 ns
  • D. 3.2 ns
  • Correct Answer: Option A

A floating-point divider, a floating-point multiplier, and a floating-point adder, are parts of a

A floating-point divider, a floating-point multiplier, and a floating-point adder, are parts of a
  • A. Floating-point multiplier
  • B. Floating-point unit
  • C. Floating-point divider
  • D. Floating-point adder
  • Correct Answer: Option B

Load instruction has a delay or latency that cannot be eliminated by forwarding, other technique used is

Load instruction has a delay or latency that cannot be eliminated by forwarding, other technique used is
  • A. Pipeline interlock
  • B. Deadlock
  • C. Stall interlock
  • D. Stall deadlock
  • Correct Answer: Option A

Set of instructions examined as candidates for potential execution is called the

Set of instructions examined as candidates for potential execution is called the
  • A. Frame
  • B. Register
  • C. Window
  • D. Blocke
  • Correct Answer: Option C

Decoding is done in parallel with reading registers, which is possiblebecause register specifiers are at a fixed location, stated technique is called a

Decoding is done in parallel with reading registers, which is possiblebecause register specifiers are at a fixed location, stated technique is called a
  • A. Variable-field decoding
  • B. Fixed-field decoding
  • C. Variable decoding
  • D. fixed decoding
  • Correct Answer: Option B

Process of letting an instruction move from instruction decode stage into execution stage of this pipeline is usually called

Process of letting an instruction move from instruction decode stage into execution stage of this pipeline is usually called
  • A. Canceling
  • B. Instruction issue
  • C. Nullifying
  • D. Branch prediction
  • Correct Answer: Option B

Situations that prevent next instruction in instruction stream, from executing during its designated clock cycle are known as

Situations that prevent next instruction in instruction stream, from executing during its designated clock cycle are known as
  • A. Pipe stage
  • B. Previous stage
  • C. Hazards
  • D. Processor cycle
  • Correct Answer: Option C

Example: number of cars per hour and is determined by how often a completed car exits assembly line, shows the

Example: number of cars per hour and is determined by how often a completed car exits assembly line, shows the
  • A. Overlapping
  • B. Through put
  • C. Pipelining
  • D. Relocation
  • Correct Answer: Option B

Hazards in pipelines can make it necessary to

Hazards in pipelines can make it necessary to
  • A. Stop pipeline
  • B. Stall pipeline
  • C. Pipeline interfaring
  • D. Both a and b
  • Correct Answer: Option B
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